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LLVMCPU

-iree-convert-to-llvmlink

Perform final conversion from Linalg/HAL/Shape/Vector/Standard to LLVMIR dialect

Optionslink

-reassociateFpReductions : Specifies if FP add and mult reductions can be reordered
-target-triple           : Code generation target triple.
-target-data-layout      : Code generation target data layout.

-iree-llvmcpu-2d-scalable-to-1d-scalablelink

Pass to replace unsupported scalable dimensions with loops.

Optionslink

-assume-arm-sme : Assume the current target is ArmSME (used for testing)

-iree-llvmcpu-assign-constant-ordinalslink

Assigns executable constant ordinals across all LLVMCPU variants.

-iree-llvmcpu-assign-import-ordinalslink

Assigns executable import ordinals across all LLVMCPU variants.

-iree-llvmcpu-check-ir-before-llvm-conversionlink

Checks CPU backend specific IR constraints (like no allocas)

Optionslink

-fail-on-out-of-bounds : Fails if the upper bound of dynamic stack allocation cannot beresolved or is more than the limit.

-iree-llvmcpu-emit-vectorization-remarkslink

Emit vectorization remarks on Linalg ops

-iree-llvmcpu-expand-f16-op-to-f32link

Preform f16 opertaions by expanding them to f32.

Pass to handel F16 bit operations, but converting f16 operands to F32. Currently this pass is handeling fmaxf conversion from f16 to f32, and then returing a f16 output back after preforming the operation. Can handle more operations if required in future.

-iree-llvmcpu-link-executableslink

Links LLVMCPU HAL executables within the top-level program module.

Optionslink

-target : Target backend name whose executables will be linked by this pass.

-iree-llvmcpu-lower-executable-targetlink

Lower executable target using an IREE::HAL::DispatchLoweringPassPipeline

Pass to lower the module an hal.executable.variant operation to external dialect. Currently this pass lowers to LLVM dialect, but could be generalized to lower to any "final" dialect like SPIR-V/NVVM, etc.

-iree-llvmcpu-mmt4d-vector-loweringlink

Apply vector lowering logic to vector ops

Optionslink

-vector-contract-custom-kernels : Flag to enable or disable vector contract custom kernels.

-iree-llvmcpu-peellink

Pass to perform peeling on non-distributed loops.

-iree-llvmcpu-select-lowering-strategylink

Select a IREE::HAL::DispatchLoweringPassPipeline for lowering the variant

Pass to select a lowering strategy for a hal.executable.variant operation. The variant is annotated with the selected strategies, which are subsequently ingested by LLVMCPULowerExecutableTargetPass.

-iree-llvmcpu-split-reductionlink

Pass to splitReduce linalg operations.

Optionslink

-enable-fp-reduction-reordering : Flag to enable reduction reordering on floating points.

-iree-llvmcpu-synchronize-symbol-visibilitylink

Synchronizes LLVM linkage with MLIR symbol visibility

-iree-llvmcpu-tilelink

Pass to tile TilingInterface operations.

Walk through all the TilingInterface operations and apply the tiling, if the given level is found in the operation's lowering config.

Optionslink

-tiling-level : Tiling level used to retrieve the configuration from lowering_config.
-skip-root-op : Do not tile the root op if the option is true.

-iree-llvmcpu-tile-and-fuse-producer-consumerlink

Pass to tile root op and fuse with producer and consumer TilingInterface ops.

Optionslink

-tiling-level                      : The tiling level used to retrieve the configuration from lowering_config
-only-fuse-producer-input-operands : Specifies if we only want to fuse producer's input operands. This is helpful to tile&fuse in case of reduction dimensions.
-anchor-on-root-op                 : Anchor on the root op to start the tiling. Otherwise, find the last operation after the root op that contains the `tilingLevel` config.

-iree-llvmcpu-tile-to-vector-sizelink

Tile TilingInterface operations to target vector size.

Walk through all the TilingInterface operations and tiling the dimensions to target vector sizes, if the lowering config is present and the dimension is known as greater than the vector size.

It is intended to be used before vectorization that avoids big vectors and stack buffers.

-iree-llvmcpu-unfuse-fma-passlink

Convert llvm.fma into unfused mulf and addf ops

-iree-llvmcpu-vector-contract-custom-kernelslink

Enable custom kernels (inline assembly or intrinsics) for some vector.contract ops

-iree-llvmcpu-vector-shape-cast-loweringlink

Pass to lower vector.shape_cast ops.

-iree-llvmcpu-vector-transpose-loweringlink

Pass to lower vector.transpose ops.

Optionslink

-lower-vector-transpose-to-avx2 : Add specific transpose to avx2 lowering patterns.

-iree-llvmcpu-verify-linalg-transform-legalitylink

Verify that only supported IR constructs are passed to the compiler.

-iree-llvmcpu-verify-vector-size-legalitylink

Signals errors when there are large vectors in the IR. I.e., one ofthe vector sizes is greater thanclMaxAllowedNumberOfNativeVectors * native_vector_size. For scalablevectors, it assumes that the vscale value is always 1. It may be anunderestimate if the runtime larger than 1, but it should still catchunreasonable vector sizes.

-iree-llvmcpu-virtual-vector-loweringlink

Pass to lower high level vector operations like contract or multidim reduce ops to lower level vector ops.

Optionslink

-split-transfers : Split vector transfers between slow (masked) and fast "
        "(unmasked) variants. Possible options are:\n"
          "\tnone [default]: keep unsplit vector.transfer and pay the price\n"
          "\tlinalg-copy: use linalg.fill + linalg.generic for the slow path\n"
          "\tvector-transfers: use extra small unmasked vector.transfers for"
          " the slow path\n
-enable-arm-i8mm : Enables arm i8mm lowering patterns